FPGA mapping algorithm based on numerical sequence matching

The FPGA logic block mapping algorithm described in this paper is based on numerical sequence matching. Numerical sequences are generated under certain rules to represent each functional circuit of the FPGA´s logic block and the user´s input circuit. The mapping procedure is conducted by matching the sequence of the input circuits and the logic block. This algorithm can be applied for different types of LUT logic blocks. The complexity of this algorithm is O(n²), where n is the sum of the net nodes of the input circuit, which requires far less running time than the similar matching algorithms. A “compact degree” is also introduced in this paper, which shows a fine result of area saving.