Through-silicon via (TSV) capacitance modeling for 3D NoC energy consumption estimation

Author

Jueping, Cai ; Peng, Jiang ; Lei, Yao ; Yue, Hao ; Zan, Li

Author_Institution

Wide Bandgap Semicond. Technol. Disciplines State Key Lab., Xidian Univ., Xi´´an, China

fYear

2010

Firstpage

815

Lastpage

817

Abstract

Three-Dimensional (3D) integration will take the next stage VLSI technology instead of 2D technology. In 3D chip, the electrical performances are much better than in 2D chip, for its short length. In this paper, an accurate energy consumption model of 3D Through-Silicon-Via (TSV) is proposed for power estimation of 3D Network- on-Chip (NoC). The capacitance model of isolated TSV is analyzed in detail, and by comparing against Monte Carlo simulations in Silvaco. About 6.9% and 10.1% error of mathematic model exists to simulation results and measurement results. By integrating the model in NoC simulator, the energy consumption of network can be estimated quickly and accurately.

Keywords

VLSI; energy consumption; network-on-chip; 3D NoC energy consumption estimation; 3D network-on-chip; Monte Carlo simulations; VLSI technology; power estimation; three-dimensional integration; through-silicon via capacitance modeling; Analytical models; Capacitance; Energy consumption; Mathematical model; Solid modeling; Three dimensional displays; Through-silicon vias; 3D; Energy Consumption; Network-on-Chip; TSV;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667434

Filename

5667434