DocumentCode
1631652
Title
The fast packet ring switch: a high-performance efficient architecture with multicast capability
Author
Rahnema, Moe
Author_Institution
GTE Lab. Inc., Waltham, MA, USA
fYear
1989
Firstpage
884
Abstract
A ring-based architecture for the packet switching of integrated traffic is presented. The architecture is nonblocking and has been designed to use the limited bandwidth of the ring interconnect most efficiently. The transmit buffers have been structured to achieve selective queuing of packets. Thus service priorities may be implemented to fairly balance the network delays among the different classes of traffic. Moreover, the current architecture has provided for the cut-through switching of packets. Quasi-circuit switching through selected ports can then be achieved with a peak bit-rate bandwidth allocation strategy. Thus hybrid integrated packet and circuit switching is made possible
Keywords
electronic switching systems; packet switching; architecture; bandwidth; bandwidth allocation; electronic switching systems; fast packet ring switch; integrated traffic; multicast; nonblocking; packet switching; Bandwidth; Delay; Laboratories; Packet switching; Routing; Switches; Switching circuits; Telecommunication switching; Throughput; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, 1989. ICC '89, BOSTONICC/89. Conference record. 'World Prosperity Through Communications', IEEE International Conference on
Conference_Location
Boston, MA
Type
conf
DOI
10.1109/ICC.1989.49816
Filename
49816
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