DocumentCode
1631696
Title
Enhanced timing-based transition delay testing for small delay defects
Author
Putman, Richard ; Gawde, Rahul
Author_Institution
Cirrus Logic, Inc., Austin, TX, USA
fYear
2006
Abstract
This paper proposes a technique for testing small delay defects that incorporates the use of standard transition delay ATPG along with timing information gathered from standard static timing analysis (STA), in order to obtain a high defect coverage of the small delay defects that lie along the critical paths of a given design. This technique takes advantage of the fact that transition delay APTG can easily create patterns for node-based delay defects, and it then uses the timing information gathered from STA to ensure that the patterns that test given paths are grouped with like patterns and are tested at near maximum frequency. We present the experimental results, which demonstrate the effectiveness of this technique to detect small delay defects using transition delay ATPG.
Keywords
automatic test pattern generation; delays; automatic test pattern generation; delay defects; static timing analysis; transition delay testing; Automatic test pattern generation; Clocks; Delay effects; Fabrication; Fault detection; Frequency; Information analysis; Logic design; Logic testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
Print_ISBN
0-7695-2514-8
Type
conf
DOI
10.1109/VTS.2006.33
Filename
1617614
Link To Document