Title :
Design of single wafer future logic fabs
Author :
Castrucci, Paul ; Griffin, Jim ; Williams, Malcolm
Author_Institution :
Paul Castrucci & Associates Inc., Cambridge, MA, USA
Abstract :
We will describe several unique, single wafer, logic fabs designed to meet the challenges of wafer processing in the 1990s. Specifically, we will compare four fab designs: (1) a new fab standard (NFS), which is designed with minienvironment Class 1 or better in the wafer processing and Class 10,000 in the support areas; (2) a more conventional Class 1 ball-room design that is smaller due to new tooling concepts; (3) a unique minienvironment, small footprint, three story production fab in which the subfloor is used for photo lithography and ion implant; (4) and a minienvironment, two story production fab, slab-on-grade design. The four fab designs will produce a minimum of 25 logic part numbers per day and will process 200 mm, 0.35 micron technology wafers at a rate of 500 wafer starts per day with four levels of metal in seven days or less
Keywords :
technological forecasting; 0.35 micron; 200 mm; Class 1; Class 10,000; ball-room design; ion implant; minienvironment; new fab standard; photo lithography; single wafer future logic fabs; slab-on-grade design; small footprint three story production fab; subfloor; tooling; two story production fab; wafer processing; Costs; Design engineering; Floors; Ice; Implants; Integrated circuit technology; Lithography; Logic design; Production; Space technology;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop. 1994 IEEE/SEMI
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-2053-0
DOI :
10.1109/ASMC.1994.588151