Metal-gate/high-к CMOS scaling from Si to Ge at small EOT

Author

Chin, Albert ; Chen, W.B. ; Shie, B.S. ; Hsu, K.C. ; Chen, P.C. ; Cheng, C.H. ; Chi, C.C. ; Wu, Y.H. ; Chaing-Liao, K.S. ; Wang, S.J. ; Kuan, C.H. ; Yeh, F.S.

Author_Institution

Electron. Eng. Dept., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2010

Firstpage

836

Lastpage

839

Abstract

Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6~1 nm EOT and low V_t of ~0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO₂/Si universal mobility at an E_eff of 1 MV/cm.

Keywords

CMOS integrated circuits; MOSFET; elemental semiconductors; germanium; high-k dielectric thin films; hole mobility; oxygen compounds; silicon; silicon compounds; Ge; SiO₂-Si; SiON; channel MOSFET; down-scaling EOT; equivalent-oxide thickness; high-κ gate dielectric; high-field hole effective mobility; metal-gate-high-κ CMOS scaling; mobility degradation reduction; ultra-thin interfacial layer; voltage 0.15 V; CMOS integrated circuits; Capacitance-voltage characteristics; Dielectrics; Electron devices; Logic gates; MOSFET circuits; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667443

Filename

5667443