Title :
Fault location in repairable programmable logic arrays
Author_Institution :
Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI
Abstract :
In order to ensure the manufacture of large PLA (programmable logic array) chips with reasonable yield level, a design for repairable PLAs (RPLAs) was proposed in which the partially defective chips can be repaired without reconfiguring the external routing. However, before a defective chip can be repaired, the locations of the defects must be precisely identified. The author presents a fault location (diagnosis) scheme that achieves a full diagnosability in locating all single and multiple stuck-at, bridging, and crosspoint faults. Two examples are given to demonstrate the proposed scheme
Keywords :
fault location; integrated circuit manufacture; integrated circuit testing; logic CAD; logic arrays; logic testing; production testing; IC testing; PLA; bridging faults; crosspoint faults; diagnosis; fault location; multiple faults; partially defective chips; repair; repairable programmable logic arrays; single faults; stuck-at faults; yield; Circuit faults; Fault detection; Fault diagnosis; Fault location; Logic design; Manufacturing; Programmable logic arrays; Routing; Shift registers; Testing;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82355
