• DocumentCode
    1631735
  • Title

    High-K dielectric stack percolation breakdown statistics

  • Author

    Sune, Jordi ; Wu, Ermest Y. ; Tous, S.

  • Author_Institution
    Dept. d´´Eng. Electron., Univ. Autonoma de Barcelona, Bellaterra, Spain
  • fYear
    2010
  • Firstpage
    1588
  • Lastpage
    1591
  • Abstract
    A cell-based analytical percolation model recently proposed for the dielectric breakdown (BD) of high-K stack gate dielectrics is reformulated in terms of competing local percolation paths. The model is equivalent to kinetic Monte Carlo implementation of percolation and it is shown to be consistent with large sample size statistical data. This is a physics-based picture that predicts the scaling of the BD distribution with the oxide area and with the thickness of each stack dielectric layer. As an application exercise, we consider the scaling of the stack reliability when the SiO2-based interface layer thickness is scaled towards zero at constant equivalent oxide thickness (EOT).
  • Keywords
    Monte Carlo methods; electric breakdown; high-k dielectric thin films; percolation; reliability; silicon compounds; SiO2; cell-based analytical percolation model; equivalent oxide thickness; high-K dielectric stack percolation breakdown statistics; interface layer thickness; kinetic Monte Carlo implementation; local percolation paths; physics-based picture; stack reliability; Analytical models; Data models; Dielectrics; High K dielectric materials; Logic gates; Reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-5797-7
  • Type

    conf

  • DOI
    10.1109/ICSICT.2010.5667444
  • Filename
    5667444