Exploiting regularity for inductive fault analysis

Inductive fault analysis is the process of determining which defects are likely to occur in an integrated circuit for a given manufacturing process. Although IFA provides a more accurate defect list for test than standard fault models, it typically retires a significant amount of computation time. We propose, a methodology that exploits the physical regularity of a design to reduce the computation time, required for IFA. This methodology was applied to several designs implemented in a via-programmable gate array (an example of a regular circuit fabric) and shown to provide an average speedup of 46times