Title :
A fast pipelined CMOS SRAM
Author :
Dickinson, Alex ; Hatamian, Mehdi ; Rao, Sailesh
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
Abstract :
A fast synchronous pipelined CMOS static random access memory (SRAM) capable of reading and writing a new address every 10 ns is described. The design incorporates several interesting techniques-in particular, a novel sense amplifier based on a critically balanced cross-coupled inverter, and associated self-timed read/write logic. A 64-kbit block has been fabricated in the 0.9-μm digital CMOS process, and tested with a cycle time of better than 10 ns. A 256-kbit version is being designed
Keywords :
CMOS integrated circuits; SRAM chips; pipeline processing; 0.9 micron; 10 ns; 256 kbit; 64 kbit; CMOS SRAM; address reading; address writing; critically balanced cross-coupled inverter; cycle time; fast synchronous pipelined CMOS static random access memory; self-timed read/write logic; sense amplifier; CMOS process; Circuit synthesis; Clocks; Decoding; Delay; Memory architecture; Pipeline processing; Random access memory; Read-write memory; Timing;
Conference_Titel :
TENCON '92. ''Technology Enabling Tomorrow : Computers, Communications and Automation towards the 21st Century.' 1992 IEEE Region 10 International Conference.
Conference_Location :
Melbourne, Vic.
Print_ISBN :
0-7803-0849-2
DOI :
10.1109/TENCON.1992.271862
