A 600 MHz 100 K ECL output buffer fabricated in 0.9 μm CMOS

Author

Gabara, Thaddeus

Author_Institution

AT&T Bell Labs., Murray Hill, NJ, USA

fYear

1992

Firstpage

774

Abstract

A 600 MHz 100 kbit emitter-coupled logic (ECL) output buffer fabricated in 0.9 μm CMOS is presented. A new circuit technique is used which dynamically adjusts both the low and high DC drive levels of the output transistor circuit. The high AC performance of the buffer is achieved by segregating the high-speed data flow from the low-speed transistor sizing control bits. This segregation occurs at a pseudo-NMOS gate-like structure which itself is reconfigured by the values of the control bits. Actual measured results of the buffer operating at 677 MHz are given

Keywords

CMOS integrated circuits; buffer circuits; emitter-coupled logic; insulated gate field effect transistors; integrated logic circuits; 0.9 micron; 100 kbit; 600 MHz; 677 MHz; AC performance; CMOS; DC drive levels; ECL output buffer; circuit technique; data segregation; emitter-coupled logic; high-speed data flow; low-speed transistor sizing control bits; output transistor circuit; pseudo-NMOS gate-like structure; structural reconfiguration; Bridge circuits; Continuous wavelet transforms; Impedance; Inverters; Low voltage; Power dissipation; Power transmission lines; Size control; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '92. ''Technology Enabling Tomorrow : Computers, Communications and Automation towards the 21st Century.' 1992 IEEE Region 10 International Conference.

Conference_Location

Melbourne, Vic.

Print_ISBN

0-7803-0849-2

Type

conf

DOI

10.1109/TENCON.1992.271865

Filename

271865