Built in self test of the Macrolan chip

The authors describe the experience of implementing self-test in the medium access controller (MAC) chip for the Macrolan advanced fiber-optic local area network system. The CMOS chip contains approximately 35K gates and 200 logic pins, and has been designed using a semi-custom-design approach based on a parameterized cell library. The implementation of BIST (built-in self-test) for this chip has highlighted problems with some conventional BIST techniques and led to the adoption of new test styles. In particular, quasi-exhaustive test has been widely used for testing combinatorial logic within the chip. Also the tradeoffs involved in testing embedded memories and the assumptions on modeling random pattern testing of such memories have been closely investigated. It is concluded that the methodology described allows ASICs (application-specific integrated circuits) to be designed with full BIST