Ultra-thin SOI wafer technologies for 22/20nm CMOS or beyond

Author

Yoshimi, Makoto ; Cauchy, Xavier ; Maleville, Christophe

Author_Institution

Soitec Asia, Tokyo, Japan

fYear

2010

Firstpage

997

Lastpage

998

Abstract

Ultra-thin SOI wafer technologies designed for 22/20nm CMOS are presented. It is stressed that planar, non-doped, and fully-depleted (FD) SOI structures are realistic options that not only solve various scaling issues, but also provide simplicity and flexibility in the device process and the circuit design. To realize 22/20nm planar FD-SOI CMOS, 300mm SOI wafer process by Smart Cut™ [1] has been optimized, focusing on the uniformity of Si film thickness, and adjusting thickness of buried oxide (BOX). It is shown that thickness variation of a 12nm-thick Si film can be controlled within +/- 2.5% for the whole wafer area. Also, buried-oxide (BOX) can be reduced down to 10nm while maintaining high bonding quality, which is expected to provide 22/20nm FD-SOI CMOS with additional advantages, such as improved short channel effect, multi-threshold voltages, and SOI-bulk hybrid structure. It is also shown that these technologies are extending planar CMOS roadmap beyond 22/20nm nodes.

Keywords

CMOS integrated circuits; elemental semiconductors; integrated circuit design; semiconductor thin films; silicon; silicon-on-insulator; wafer bonding; BOX; CMOS technology; FD SOI structure; Smart Cut; bonding quality; buried oxide; circuit design; film thickness; fully-depleted SOI structure; nondoped SOI structure; planar SOI structure; size 20 nm; size 22 nm; ultra-thin SOI wafer technology; Analog circuits; CMOS integrated circuits; CMOS technology; Films; Scalability; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667514

Filename

5667514