DocumentCode :
1633798
Title :
Wafer fab construction cost analysis and cost reduction strategies: applications of SEMATECH´s future factory analysis methodology
Author :
Art, David ; O´Halloran, Michael ; Butler, Brian
Author_Institution :
SEMATECH, Austin, TX, USA
fYear :
1994
Firstpage :
16
Lastpage :
21
Abstract :
This paper discusses semiconductor wafer fabrication (fab) factory construction costs as they relate to emerging technologies. The generation of factories studied represents facilities supporting 200 mm wafers, and products utilizing 0.25 micron line-width geometries. An analytical approach to categorizing and evaluating fab costs is presented. A pareto analysis of four recent factories´ costs is presented. The organization of fab construction costs into ten useful assemblies is reviewed and explained. Examination of the cost categories shows that of approximately 200 categories, 23 categories account for approximately 60 percent of the overall construction costs. Potential strategies focusing on reducing construction costs are illustrated. The concepts and data for this paper have been developed from SEMATECH´s work with Industrial Design Corporation, the engineering firm contracted to provide engineering services on the SEMATECH Facilities Future Factory Design Program
Keywords :
economics; 0.25 micron; 200 mm; Industrial Design Corporation; SEMATECH; emerging technologies; facilities; factory construction costs; future factory design; pareto analysis; semiconductor wafer fabrication; Assembly systems; Buildings; Costs; Data engineering; Design engineering; Manufacturing; Pareto analysis; Production facilities; Ultra large scale integration; Water storage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop. 1994 IEEE/SEMI
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-2053-0
Type :
conf
DOI :
10.1109/ASMC.1994.588160
Filename :
588160
Link To Document :
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