Title :
Automatic test generation algorithms based on chaotic neural network
Author :
Xie, Hua ; Wang, Houjun
Author_Institution :
Coll. of Mechatronics Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
A test generation system based on a digital circuit´s neural network model is described. A fault is injected into the neural network and an energy function is constructed with global minima at test vectors. Global minima are determined by the chaotic neural network method employing four different algorithms, and the algorithms are compared in test-time and test-figure. Simulation results on combinational circuits confirm the feasibility of this technique.
Keywords :
automatic test pattern generation; circuit simulation; circuit testing; combinational circuits; digital circuits; logic testing; neural nets; ATPG; automatic test generation algorithms; automatic test pattern generation; chaotic neural network model; combinational circuits; digital circuit; energy function; global minima; test vectors; test-figure; test-time; Automatic test pattern generation; Automatic testing; Cellular neural networks; Chaos; Circuit faults; Circuit testing; Hopfield neural networks; Neural networks; Neurons; System testing;
Conference_Titel :
Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on
Print_ISBN :
0-7803-8647-7
DOI :
10.1109/ICCCAS.2004.1346368
