DocumentCode
1633967
Title
Noise analysis of ESD structures and impacts on a fully-integrated 5.5 GHz LNA in 0.18/spl mu/m SiGe BiCMOS
Author
Chen, Guang ; Feng, Haigang ; Wang, Albert ; Cheng, Yuhua
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL
fYear
2005
Firstpage
261
Lastpage
263
Abstract
ESD-induced parasitics are critical to RF ICs. This paper reports the first quantitative study of noises of ESD protection structures and their influences on RF ICs. Noise figures (NF) of typical ESD structures were characterized and their impact on a single-chip 5.5 GHz LNA circuit was investigated. The design was implemented in a 0.18mum SiGe BiCMOS. Measurement shows substantial degradation in NF of LNA due to ESD noises and a practical selection criterion in designing RF IC with ESD structures is provided
Keywords
BiCMOS integrated circuits; Ge-Si alloys; electrostatic discharge; microwave integrated circuits; semiconductor materials; 5.5 GHz; ESD protection structures; ESD-induced parasitics; SiGe; electrostatic discharge protection design; noise analysis; noise figures; BiCMOS integrated circuits; Circuit noise; Electrostatic discharge; Germanium silicon alloys; Integrated circuit noise; Noise figure; Noise measurement; Protection; Radio frequency; Silicon germanium;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Technology, 2005. The European Conference on
Conference_Location
Paris
Print_ISBN
2-9600551-1-X
Type
conf
DOI
10.1109/ECWT.2005.1617707
Filename
1617707
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