A parallel VLSI floorplanning algorithm using corner block list topological representation

Floorplanning is a critical phase in the physical design of VLSI circuits and has been acknowledged as a computation-intensive process. As a result, several research efforts have been undertaken to parallelize the algorithm. While previous work has been focused on slicing the floorplan, we present a parallel algorithm for a non-slicing floorplan using corner block list (CBL) topological representation. A parallel interconnection cost calculation algorithm with load balancing strategy is initiated in order to speed up the especially time consuming wire length calculation in floorplanning. A multiple Markov chains strategy is also embedded in our algorithm. The experimental results obtained from the tests on MCNC benchmarks indicate considerable speedup and preserved floorplanning quality.