Title :
A new graph-theoretic formulation for VLSI floorplan design
Author :
Al-Hakim, Latif A.
Author_Institution :
Dept. of Mech. Eng., Monash Univ., Clayton, Vic., Australia
Abstract :
A new graph-theoretic formulation for floorplan design is introduced. The VLSI modules with their wire connections are represented as a weighted complete graph in which dummy edges are inserted between unconnected modules. The problem can be seen as one of extracting a maximal planar weighted subgraph from this graph. An operation referred to as the Γ-operation is presented. It is used to develop an improvement procedure. The procedure is illustrated using an example
Keywords :
VLSI; graph theory; VLSI modules; floorplan design; graph theory; maximal planar weighted subgraph; weighted complete graph; wire connections; Algorithm design and analysis; Circuit synthesis; Design engineering; Graph theory; Integrated circuit interconnections; Iterative algorithms; Minimization methods; Routing; Very large scale integration; Wires;
Conference_Titel :
TENCON '92. ''Technology Enabling Tomorrow : Computers, Communications and Automation towards the 21st Century.' 1992 IEEE Region 10 International Conference.
Conference_Location :
Melbourne, Vic.
Print_ISBN :
0-7803-0849-2
DOI :
10.1109/TENCON.1992.271966
