Logic synthesis system with standard GBAW patterns as building units

Most traditional logic synthesis systems regard simple logic gates as the basic building units. Owing to insufficient information on redundancy addition and removal of the synthesized circuits, efficient post-synthesis rewiring schemes have been developed to determine the rewiring set. Consequently the rewiring information can be utilized for logic optimization. In this paper a new approach for logic synthesis with standard graph-based alternative wiring (GBAW) patterns as building units has been proposed. The system aims at enhancing the GBAW composition in a circuit. The rewiring information of GBAW patterns can then be readily applied after the synthesis process for logic optimization such as timing optimization. Experiments showed that this approach can increase the number of GBAW local-1 and local-2 patterns for various MCNC benchmarks by 105 % and 64.5 % respectively, while the overall rise is 99.7 %.