Title :
Design for testability and test generation for static redundancy system level fault-tolerant circuits
Author :
Stroud, Charles E. ; Barbour, Ahmed E.
Author_Institution :
AT&T Bell Labs., Naperville, IL, USA
Abstract :
The necessary conditions for designing testable static redundancy system-level fault-tolerant circuits are derived. In addition, algorithms are proposed for the efficient generation of test patterns for fault-tolerant circuits designed to satisfy these testability conditions. The test generation algorithm has been incorporated with an algorithm for the construction of majority voting devices and automated to produce a software package that generates testable fault-tolerant circuits along with test patterns to test the resultant circuit completely. As input, the algorithm requires a testable original circuit, along with an associated set of test patterns and the desired design parameters E, R, and K
Keywords :
automatic testing; digital integrated circuits; fault tolerant computing; logic CAD; logic testing; redundancy; algorithms; logic CAD; logic testing; majority voting devices; software package; static redundancy system level fault-tolerant circuits; test generation; test patterns; testability; Algorithm design and analysis; Automatic test pattern generation; Automatic testing; Circuit testing; Design for testability; Fault tolerance; Redundancy; Software algorithms; Software testing; Test pattern generators;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82370
