Title :
An obstacle detoured routing algorithm based on the enhanced ACS
Author :
Yang, Bo ; Yu, Juebang ; Yan, Tan ; Li, Jing
Author_Institution :
Sch. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
The ACS (ant colony system) algorithm is quite suited for solving the obstacle detoured routing (ODR) problem in the physical design of VLSI circuits. But with the rapid growth of the number of circuit modules, the solution space of primitive ACS is substantially increased. In this paper, we present an heuristic algorithm based on an enhanced ACS to reduce the search space and accelerate the convergence. Firstly, this algorithm initializes the pheromone of a grid graph of a BBL (building block layout) mode layout respectively with an out of usual strategy. After that, we complete the main routing process based on the ACS algorithm with the heuristic of initial pheromone and obtain a feasible solution. In order to accelerate the convergence of primitive ACS, we developed a fast approach called the PEAK-CUT algorithm to shorten the path length. Taking advantage of its merits, we are able to get a local optimum solution closest to that feasible solution quickly. Comparative simulation experiments with respect to the original ACS demonstrate that our enhanced approach is superior to the ACS-only approach in several aspects, such as yielding better quality of solution, faster convergence and resulting in higher complete rate of routing.
Keywords :
VLSI; circuit optimisation; convergence of numerical methods; integrated circuit layout; network routing; BBL; PEAK-CUT algorithm; VLSI circuit design; ant colony system; building block layout; convergence acceleration; enhanced ACS; grid graph pheromone; grid routing; local optimum solution; obstacle detoured routing algorithm; out of usual strategy; path length reduction; search space reduction; Acceleration; Algorithm design and analysis; Artificial neural networks; Computer integrated manufacturing; Heuristic algorithms; Integrated circuit technology; Integrated circuit yield; Routing; Space technology; Very large scale integration;
Conference_Titel :
Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on
Print_ISBN :
0-7803-8647-7
DOI :
10.1109/ICCCAS.2004.1346408