DocumentCode
1635122
Title
Efficient 2-D systolic array implementation of a prime factor DFT algorithm
Author
Wang, Chin-Liang ; Chang, Yu-Thi
Author_Institution
Inst. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
1992
Firstpage
56
Abstract
A new two-dimensional systolic array for computing the discrete Fourier transform (DFT), with length N decomposable into the product of two relatively prime factors, 4M 1 and M 2, is presented. The architecture is constructed based on the row-column algorithm. It does not include any intermediate circuit for arranging data flow between the row-DFT and column-DFT modules. The system possesses the features of regularity and modularity, and is well suited to VLSI implementation. It has an efficiency of 100%, a throughput rate of one N -point transform per M 2 cycles, and an area×time2 figure of AT2 =O ((M 1+M 2)M 2N log22N ), which is much smaller than the value of O (N 3 log22N ) achieved by existing linear systolic array solutions
Keywords
VLSI; fast Fourier transforms; systolic arrays; 2-D systolic array; VLSI implementation; discrete Fourier transform; prime factor DFT algorithm; row-column algorithm; Arithmetic; Circuits; Computer architecture; Digital signal processing; Discrete Fourier transforms; Hardware; Multidimensional systems; Signal processing algorithms; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON '92. ''Technology Enabling Tomorrow : Computers, Communications and Automation towards the 21st Century.' 1992 IEEE Region 10 International Conference.
Conference_Location
Melbourne, Vic.
Print_ISBN
0-7803-0849-2
Type
conf
DOI
10.1109/TENCON.1992.271984
Filename
271984
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