Constraints generation for analog circuits layout

In this paper, we present constraint definitions, how to extract them, the existing extraction methods, and our methods. Because the analog signal is sensitive to noise and parasitics, various layout constraints have to be taken into account in the design of high performance analog circuits. In this paper, two methods are proposed to extract these layout constraints from analog circuits, such as grouping, symmetry and matching. Circuits are represented as bipartite graphs. Group constraints among devices are generated by means of signal flow analysis on the circuit. Symmetry constraints are extracted by solving graph isomorphism. Matching constraints can be generated by pattern recognition. The experimental results demonstrate the effectiveness and efficiency of the proposed methods.