Constraints generation for analog circuits layout

Because analog signals are sensitive to noise and parasitics, various layout constraints have to be taken into account in the design of high performance analog circuits. We present constraints´ definitions, how to extract them, existing extraction methods, and our methods. Two methods are proposed to extract the layout constraints from analog circuits, such as grouping, symmetry and matching. Circuits are represented as bipartite graphs. Group constraints among devices are generated by means of signal flow analysis on the circuit. Symmetry constraints are extracted by solving graph isomorphism. Matching constraints can be generated by pattern recognition. Experimental results demonstrate the effectiveness and efficiency of the proposed methods.