Title :
A 33 Mflops Floating Point Processor Using Redundant Binary Representation
Author :
Edamatsu, H. ; Taniguchi, T. ; Nishiyama, T. ; Kuninobu, S.
Author_Institution :
Matsushita Semiconductor Research Center, Osaka, Japan
Keywords :
Adders; Arithmetic; Circuits; Clocks; Delay; Ducts; Pipeline processing; Process design; Registers;
Conference_Titel :
Solid-State Circuits Conference, 1988. Digest of Technical Papers. ISSCC. 1988 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1988.663676
