Title :
On the design and test of asynchronous macros embedded in synchronous systems
Author :
Leenstra, Jens ; Spaanenburg, Lambert
Author_Institution :
Inst. for Microelectron., Stuttgart, West Germany
Abstract :
The design of synchronously testable asynchronous macros is investigated. A novel implementation model which uses an explicit state register is presented. This approach makes it possible to apply scan and boundary tests to nonsynchronous VLSI systems. The state register is composed of SR (set-reset) flip-flops, which can operate in asynchronous, synchronous, and (token) scan mode. It is shown that these controllers are synchronously testable and can be derived directly from a control graph description. The approach is exemplified by the design and test of a self-timed ALU (arithmetic and logic unit)
Keywords :
VLSI; asynchronous sequential logic; flip-flops; integrated circuit testing; integrated logic circuits; logic CAD; logic testing; arithmetic and logic unit; boundary tests; control graph; explicit state register; nonsynchronous VLSI systems; scan tests; self-timed ALU; set reset flip flops; synchronously testable asynchronous macros; token scan; Automata; Automatic testing; Circuit testing; Design for testability; Latches; Logic testing; Microelectronics; Strontium; System testing; Very large scale integration;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82373
