An Architecture of Dynamically Reconfigurable Processing Unit(RPU)

Reconfigurable system can offer considerably higher performance than general purpose processors and are, in addition, significantly more flexible than application-specific systems. The efficient coarse-grained dynamically reconfigurable processing unit is the key feature of the reconfigurable system. In this paper, a novel dynamically reconfigurable processing unit (RPU) is proposed in order to improve the flexibility and adaptability of the general processing element(PE). By dynamic configuration of the configurable register(Creg), the proposed RPU can process complex number(8-bit real part and imaginary part) and 16-bit fixed number ( unsigned-magnitude or 2 ´s complement data). The operation of 8-bit complex number multiply-accumulation is performed in a single clock cycle. Therefore, two RPUs working together can execute butterfly computation in a single clock cycle. Based on Charter 0.25um standard cell library, the area of RPU is 0.< 16ns.