DocumentCode
163608
Title
High performance n+/p junction technology for high mobility Ge nMOSFET
Author
Chin, Alvin ; Shih-Han Yi
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2014
fDate
18-20 May 2014
Firstpage
1
Lastpage
4
Abstract
Power consumption is the most crucial challenge for advanced IC with billions of transistors. High mobility Ge CMOS is one of the promising candidates to further lower the power consumption. Unfortunately, the ohmic contact in Ge nMOSFET suffers from Fermi-level pinning to valance band (Ev). It is also hard to form n+/p Ge junction by standard ion implantation due to the poor dopant activation by rapid thermal annealing (RTA) and fast impurity diffusion. Here high performance metal-gate/high-k/(111)-Ge nMOSFET was achieved with good 1.05 junction ideality factor (n), large ~5 orders on/off junction current, and higher mobility than SiO2/Si data at wide range carrier density (Ns) at small 0.85 nm equivalent-oxide thickness (EOT). The excellent n+/p Ge junction is attributed to the fast 30-ns laser annealing (LA) and YbGe2-x/n-Ge contact with less Fermi-level pinning.
Keywords
Fermi level; MOSFET; carrier density; germanium; ion implantation; laser beam annealing; ohmic contacts; p-n junctions; rapid thermal annealing; silicon compounds; ytterbium compounds; Fermi level pinning; Ge; RTA; SiO2-Si; YbGe2-x-Ge; carrier density; fast impurity diffusion; high mobility CMOS; high mobility nMOSFET; ion implantation; junction ideality factor; laser annealing; n+/p junction technology; ohmic contact; on-off junction current; power consumption; rapid thermal annealing; time 30 ns; CMOS integrated circuits; Junctions; MOS devices; MOSFET circuits; Ohmic contacts; Power demand; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Junction Technology (IWJT), 2014 International Workshop on
Conference_Location
Shanghai
Type
conf
DOI
10.1109/IWJT.2014.6842048
Filename
6842048
Link To Document