Title :
Hardware implementation of maximum Lyapunov exponent
Author :
De Micco, Luciana ; Antonelli, Maximiliano ; Gonzalez, C.M. ; Larrondo, Hilda A.
Author_Institution :
Dept. de Fis. y de Ing. Electron., Univ. Nac. de Mar del Plata, Mar del Plata, Argentina
Abstract :
In this paper a hardware implementation of a Maximum Lyapunov Exponent (MLE) quantifier is designed and implemented using a field programmable gate array (FPGA). The design was optimized in terms of accuracy employing floating point architecture to represent the values. The proposed design takes advantage of the underline parallelism of the MLE computation equations and allows its concurrent implementation based on FPGA technology.
Keywords :
field programmable gate arrays; floating point arithmetic; parallel processing; FPGA; MLE computation equations; MLE quantifier; field programmable gate array; floating point architecture; hardware implementation; maximum Lyapunov exponent quantifier; parallelism; Chaos; Field programmable gate arrays; Hardware; Maximum likelihood estimation; Phase locked loops; Timing; Trajectory;
Conference_Titel :
Embedded Systems (SASE/CASE), 2013 Fourth Argentine Symposium and Conference on
Conference_Location :
Buenos Aires
Print_ISBN :
978-1-4799-1098-4
DOI :
10.1109/SASE-CASE.2013.6636776
