High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications

Author

Jonghae Kim ; Plouchart, J.-O. ; Zamdmer, N. ; Fong, N. ; Liang-Hung Lu ; Yue Tan ; Jenkins, K.A. ; Sherony, M. ; Groves, R. ; Kumar, M. ; Ray, A.

Author_Institution

Dev. Center, IBM Semicond. Res., Hopewell Junction, NY, USA

Volume

1

fYear

2003

Abstract

This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 /spl mu/m SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH//spl mu/m/sup 2/ is obtained for a 42 nH MTS (Multi-turn, multiple metal layers in Series) inductor.

Keywords

CMOS integrated circuits; Q-factor; copper; equivalent circuits; integrated circuit technology; radiofrequency integrated circuits; silicon-on-insulator; thin film inductors; 0.12 micron; 3D on-chip inductors; 5 GHz; Cu; Cu metal layers; MTS inductor; RFIC; SOI CMOS technology; STP inductor; Si; high-Q inductors; high-inductance-density inductors; high-performance on-chip inductors; high-resistivity substrate; monolithic RF circuit applications; three-dimensional on-chip inductors; CMOS technology; Circuits; Conductivity; Copper; Geometry; Inductance; Inductors; Predictive models; Q measurement; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2003 IEEE MTT-S International

Conference_Location

Philadelphia, PA, USA

ISSN

0149-645X

Print_ISBN

0-7803-7695-1

Type

conf

DOI

10.1109/MWSYM.2003.1211038

Filename

1211038