Title :
Key design techniques of a 40 ns 16 Kbit embedded EEPROM memory
Author :
Xu, Fei ; He, Xiangqing ; Zhang, Li
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
A 2K×8 bit EEPROM memory, which operates with a single 3.3 V power supply based on SMIC 0.35 μm EEPROM process, has been developed. Several key design techniques are summarized. An improved read out circuit that consists of SA (sense amplifier), bit line decoding and an optimized logic circuit to minimize the read access time, is described particularly, as well as the approaches to optimize the program operation and to generate on-chip high voltage. A 40 ns typical read access time and 2 ms page programming time are achieved. The active and standby currents are 10 mA and 100 μA respectively.
Keywords :
EPROM; amplifiers; embedded systems; integrated circuit design; integrated logic circuits; integrated memory circuits; logic design; minimisation; 0.35 micron; 10 mA; 100 muA; 16 Kbit; 2 ms; 3.3 V; 40 ns; bit line decoding; embedded EEPROM memory; logic circuit; page programming time; program operation optimization; read access time minimization; read out circuit; sense amplifier; Charge pumps; Circuits; Decoding; EPROM; Latches; Operational amplifiers; Parallel programming; Parasitic capacitance; Switches; Voltage;
Conference_Titel :
Communications, Circuits and Systems, 2004. ICCCAS 2004. 2004 International Conference on
Print_ISBN :
0-7803-8647-7
DOI :
10.1109/ICCCAS.2004.1346462
