Title :
A floating point rectangular systolic array on a chip
Author :
Clarke, R.J. ; Curtis, I.A. ; Clarke, A.P. ; Marwood, W.
Author_Institution :
RADLogic PTY Ltd., Technology Park, SA, Australia
Abstract :
The logical design and architecture of a floating point systolic array on a chip are described. The layout is presented, with a microphotograph of a functional chip fabricated in a 1 μm CMOS process. The instruction set of the chip is described, and its application to matrix operations is discussed. The chip will function either in isolation or in a cascaded one- or two-dimensional array. In these latter configurations it will be possible to build processing nodes with computing rates in excess of 1 Gflops
Keywords :
CMOS integrated circuits; digital arithmetic; digital signal processing chips; systolic arrays; 1 micron; CMOS; floating point rectangular systolic array; instruction set; layout; logic architecture; logical design; matrix operations; processing nodes; Array signal processing; Australia; Clocks; Computer aided instruction; Frequency; Laboratories; Registers; Signal design; Systolic arrays; Very large scale integration;
Conference_Titel :
TENCON '92. ''Technology Enabling Tomorrow : Computers, Communications and Automation towards the 21st Century.' 1992 IEEE Region 10 International Conference.
Conference_Location :
Melbourne, Vic.
Print_ISBN :
0-7803-0849-2
DOI :
10.1109/TENCON.1992.272041
