A VLSI architecture for salt-and-pepper filtering of classified images at video rates

An algorithm and VLSI architecture are described for salt-and-pepper filtering classified images. Small regions are reclassified to the mode of the class values in an n×n neighborhood window. An architecture has been developed that is scalable to neighborhood windows of reasonable size and still operates at video rates. The system contains multiple pipeline stages and incorporates a novel pipeline for computing the cumulative frequencies used to find the mode. The architecture has been simulated at both the functional and the transistor level to verify algorithm performance and obtain speed and area estimates. The filter will fit onto a 7×7 mm die using a 2 μ CMOS process