Title :
Synthesis of self-clocked asynchronous state machines
Author_Institution :
Dept. of Electr. & Electron. Eng., Bristol Univ., UK
Abstract :
A systematic approach to the design of asynchronous state machines with minimum state variables and arbitrary state encoding is described. Multiple input changes are allowed. Simple latches in master-slave configuration are used as memory elements rendering the method suitable for implementation in small scale integration (SSI) or VLSI. It avoids extra delay elements often necessary in self-clocked circuits. The method is illustrated by its application to the design of a VMEbus requester
Keywords :
asynchronous sequential logic; sequential circuits; system buses; SSI; VLSI; VMEbus requester; design; latches; master-slave configuration; memory elements; self-clocked asynchronous state machines; small scale integration; state encoding; state variables; Clocks; Delay; Design methodology; Hardware; Hazards; Latches; Logic design; Master-slave; Programmable logic devices; Very large scale integration;
Conference_Titel :
TENCON '92. ''Technology Enabling Tomorrow : Computers, Communications and Automation towards the 21st Century.' 1992 IEEE Region 10 International Conference.
Conference_Location :
Melbourne, Vic.
Print_ISBN :
0-7803-0849-2
DOI :
10.1109/TENCON.1992.272043
