Title :
The economics of scan design
Author_Institution :
Illinois Univ., Urbana, IL
Abstract :
The authors present a model that allows the designer to calculate the cost of scan-path design for testability (DFT) for standard cell-based chips. The model is used to estimate the profitability of designs that use DFT techniques over the product life cycle and those that do not. It is shown that, under dynamic market conditions, it is sometimes better to choose a more expensive solution if the product can be delivered faster. Thus, scan-path techniques can more than make up for their extra area if they reduce test generation time and therefore product lead times
Keywords :
VLSI; economics; integrated circuit testing; integrated logic circuits; logic testing; production testing; IC testing; VLSI; cost; design for testability; economics; logic testing; product lead times; product life cycle; profitability; scan design; scan-path; standard cell-based chips; test generation time; Circuit testing; Costs; Design for testability; Design methodology; Engineering management; Flip-flops; Product design; Profitability; Sequential analysis; Software testing;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82377
