Title :
Burst cycle data compression schemes for pre-fuse wafer-level test in large scale high-speed embedded DRAM
Author :
Fukuda, R. ; Kobayashi, K. ; Akamatsu, M. ; Kaihatsu, M. ; Tamura, A. ; Taniguchi, K. ; Watanabe, Y.
Author_Institution :
Toshiba Corp. Semicond. Co., Kanagawa, Japan
Abstract :
This paper describes two novel data compression schemes suitable for high density and high speed embedded DRAMs. The parallel compression serial readout scheme reduces bit-scan test times to one eighth. The parallel compression multiplexed readout scheme realizes high frequency at-speed tests even with low cost testers. Both can be used for pre-fuse wafer tests requiring redundancy calculations. The new schemes have been implemented in a test chip with a 65nm technology and verified.
Keywords :
DRAM chips; data compression; redundancy; 65 nm; burst cycle data compression schemes; large scale high-speed embedded DRAM; parallel compression multiplexed readout scheme; pre-fuse wafer tests; pre-fuse wafer-level test; redundancy calculations; Built-in self-test; Clocks; Costs; Data compression; Frequency; Large-scale systems; Performance evaluation; Random access memory; Testing; Timing;
Conference_Titel :
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8287-0
DOI :
10.1109/VLSIC.2004.1346491
