A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

Author

Soh, Young-Soo ; Choi, Jung-Hwan ; Chung, In-Young ; Chung, Hoeju ; Kim, Chan-Kyoung ; Byun, Gyoung-Su ; Kang, Dae-Woon ; Park, Won-Ki ; Park, In-Soo ; Hwang, Hong-Sun ; Kim, Chang-Hyun ; Cho, Soo-In

Author_Institution

Memory Div., Samsung Electron. Co., Hwasung, South Korea

fYear

2004

Firstpage

36

Lastpage

37

Abstract

A 1.8V, 512Mbit Packet-based DRAM with 3.2Gbps/pin was designed for main memory of a game console and graphic application. To have lower power consumption and smaller area in clock generation and distribution, 3-row pad structure with reduced clock loading and PLL with loop zero from voltage offset are used. An analytical equation for estimating the input capacitance of pad with ODT (On-Die Termination) is also presented.

Keywords

DRAM chips; synchronisation; voltage-controlled oscillators; 3.2 Gbit/s; 3.2Gbps/pin packet-based DRAM; 512 Mbit; cost-efficient clock generation; distribution scheme; game console; graphic application; lower power consumption; memory; Capacitance; Charge pumps; Clocks; Filters; Graphics; Phase locked loops; Power generation; Random access memory; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8287-0

Type

conf

DOI

10.1109/VLSIC.2004.1346493

Filename

1346493