Low-power and robust 6T SRAM cell using symmetric dual-k spacer FinFETs

Author

Pal, Pankaj Kumar ; Kaushik, B.K. ; Dasgupta, S.

Author_Institution

Dept. of Electron. & Commun. Eng., Indian Inst. of Technol.-Roorkee, Roorkee, India

fYear

2014

fDate

12-14 May 2014

Firstpage

103

Lastpage

106

Abstract

This paper proposes a dual-k spacer FinFET architecture that shows superior electrostatic integrity over the conventional low-k spacer underlap device and thus suppress SCEs. Furthermore, the proposed dual-k structure explores the possibility of symmetric FinFETs that helps to augment all SRAM design metrics without affecting cell-ratio and pull-up ratio.

Keywords

MOSFET; SRAM chips; low-power electronics; SCE; SRAM design metrics; cell-ratio; electrostatic integrity; low-k spacer underlap device; low-power; pull-up ratio; robust 6T SRAM cell; short channel effects; symmetric dual-k spacer FinFET; Computer architecture; Electrostatics; FinFETs; High K dielectric materials; Logic gates; Measurement; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics Proceedings - MIEL 2014, 2014 29th International Conference on

Conference_Location

Belgrade

Print_ISBN

978-1-4799-5295-3

Type

conf

DOI

10.1109/MIEL.2014.6842096

Filename

6842096

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=163696