A 4GHz Fractional-N synthesizer for IEEE 802.11a

Phase noise of the Fractional-N synthesizer depends critically on the linearity of its building blocks. In this research, new design methods are shown to directly improve its linearity. This includes a new re-timing scheme that effectively reduces phase noise for multi-modulus dividers. Further reductions in phase noise result from introduction of a high linearity CMOS charge pump. Measurement results verify the concept and demonstrate low phase noise performance at 4GHz.