DocumentCode :
1637107
Title :
Design-for-testability using test design yield and decision theory
Author :
Kaminska, Bozena ; Savaria, Yvon
Author_Institution :
Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
fYear :
1989
Firstpage :
884
Lastpage :
892
Abstract :
A framework for prediction and estimation of the test yield and test cost of VLSI systems during the design-for-testability stage is given. As an important extension, the authors present a technique for evaluating the set of possible solutions and selecting the most effective one. This technique is based on the evaluation of test-related performance measures and on decision theory. As a result, a new level of design and test integration is obtained. Experimental results have confirmed the applicability and effectiveness of the method. It is shown that it is possible to derive, in a very straightforward manner, maximum and minimum expected values of the design yields of a strategy (design scheme)
Keywords :
VLSI; circuit CAD; decision support systems; economics; integrated circuit testing; integrated logic circuits; logic CAD; ASIC; IC testing; VLSI; decision theory; design-for-testability; estimation; logic CAD; prediction; test cost; test design yield; Application specific integrated circuits; Automatic testing; Circuit testing; Costs; Decision making; Decision theory; Design automation; Design for testability; Process design; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
Type :
conf
DOI :
10.1109/TEST.1989.82379
Filename :
82379
Link To Document :
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