• DocumentCode
    1637385
  • Title

    A calibration-free 3V 16b 500kS/s 6mW 0.5mm2 ADC with 0.13 μm CMOS

  • Author

    Choi, Hee-Cheol ; You, Seung-Bin ; Lee, Ho-Young ; Park, Ho-Jin ; Kim, Jae-Whui

  • Author_Institution
    Samsung Electron. Co. Ltd., Yongin, South Korea
  • fYear
    2004
  • Firstpage
    76
  • Lastpage
    77
  • Abstract
    A calibration-free 3V 6mW 16-bit 500kS/s cyclic ADC with an active die area of 0.5mm2 is implemented in a 0.13 μm CMOS. The proposed converter adopts a 2.5-bit/stage cyclic architecture and capacitor layout scheme to achieve improved matching accuracy, the DNL and INL of ±0.90 LSB and ±6.1 LSB, respectively.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; 0.13 μm CMOS; 0.13 micron; 3 V; 6 mW; active die area; bit/stage cyclic architecture; calibration-free ADC; capacitor layout scheme; converter; improved matching accuracy; CMOS process; Circuits; Clocks; Energy consumption; Error correction; MIM capacitors; Parasitic capacitance; Routing; Sampling methods; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
  • Print_ISBN
    0-7803-8287-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.2004.1346509
  • Filename
    1346509
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1637385