A ultra-fast load regulation capacitor-free LDO with advanced capacitive-coupling feedforward compensation

A low-power, capacitor-free low-dropout regulator (LDO) with Pseudo-Input stage feedforward compensation (PISFFC) is proposed in this paper. This novel FFC technique, employing the method of capacitive-coupling to provide large dynamic current for driving power transistor, is highly integrated, widely applicable and can provide ultra-fast load transient response. Compared to conventional slew rate enhancement(SRE) technique, the proposed technique is power-saving and can work at lower supply voltage. Moreover, with an additional left-half plane (LHP) zero generated by PISFFC, frequency compensation can be simpler and the unity-gain-bandwidth (UGB) can be wider. A 50-mA LDO with a 0.2-nF on-chip capacitor employed the proposed PISFFC has been implemented and simulated in a 0.13μm CMOS process. Simulation results show that the LDO got low quiescent current(17μA), low-voltage operation ability(1.5V) and greatly improved transient response(output dips less than 170-mV in 0.1μs Switching time).