Drain current modelling in silicon MOSFETs

Author

Lakhlef, A. ; Benfdila, A.

Author_Institution

Microelectron. & Nanotechnol. Res. Group GRMNT, Univ. M. Mammeri, Tizi-Ouzou, Algeria

fYear

2014

fDate

12-14 May 2014

Firstpage

213

Lastpage

216

Abstract

The present paper deals with the modeling of silicon MOSFET in the variety of channel range from submicron to nanoMOSFET aiming the study of the degradation and aging of MOSFET transistor used in VLSI Integrated circuits. The proposed model can be used for better understanding of the device reliability in the operating regions of interest. Moreover, it can be seen as a characterization tool for extracting more information on the interface Si-SiO₂, the channel and the oxide itself. The model is expressed as current versus voltage in the possible full range of gate voltage and meant to comply with the unified current model.

Keywords

MOSFET; ageing; elemental semiconductors; semiconductor device models; semiconductor device reliability; silicon; silicon compounds; MOSFET transistor aging; MOSFET transistor degradation; Si-SiO₂; VLSI integrated circuits; device reliability; drain current modelling; gate voltage; nanoMOSFET; silicon MOSFETs; submicronMOSFET; unified current model; Data models; Integrated circuit modeling; Logic gates; MOSFET; Microelectronics; Reliability; Semiconductor device modeling; Carrier Mobility; Current Model; I-V Characteristic; MOSFET; Operating Regimes;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics Proceedings - MIEL 2014, 2014 29th International Conference on

Conference_Location

Belgrade

Print_ISBN

978-1-4799-5295-3

Type

conf

DOI

10.1109/MIEL.2014.6842124

Filename

6842124