Data mining techniques for a functional verification of SoC

A typical System-on-Chip integrates many blocks including peripheral IPs, buses, complex interconnects, multiple processors, memory, clock and power distribution, test structures, and buses. There are always several master blocks on the bus, resulting in complex bus architectures. That is why new system level approach in design and verification has been recently suggested in EDA industry. Despite the rising the abstraction level it is still hard to manage and analyze simulation data. This data can be archived for later use or it can be mined to look for different kind of violations or to get statistical information about the specified design. The paper describes the powerful data mining techniques within transaction level modeling for a functional verification of System-on-a-Chip models. As the result of applying new data mining techniques it is possible to gain engineer´s understanding level of model and provide transactional data analysis. Moreover, the frequency patterns can be mined from simulation data to provide the transactional debugging feature.