Design of an ultra-low power SAR ADC for biomedical applications

In this paper, an ultra-low power 12-bit 2 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented. For power optimization, the voltage supply of the digital part is lowered, and the offset voltage of the latch is self-calibrated. Targeted for lower noise, a low kick-back noise latch is proposed. The chip was fabricated using 0.18 μm 1P6M CMOS technology. The ADC achieves SNDR of 61.8 dB and dissipates only 455 nW, resulting in a figure of merit (FOM) of 220 fJ/conversion-step. The ADC core occupies an active area of 674×639 μm².