1637659

An Experimental 1mb Cmos Sram with Configurable Organization and Operation

Hsing-San Lee ; El Kareh, B. ; Flaker, R.C. ; Gravenities, G.G. ; Lipa, R.A. ; Maslack, J.P. ; Pessetto, J.R. ; Pokorny, W.F. ; Roberge, M.A. ; Williams, T. ; Zeller, H.A. ; Beilstein, K.E.

IBM General Technology Division, Essex Junction, VT

1988

180

CMOS logic circuits; CMOS process; Clocks; Decoding; Pulse amplifiers; Pulse circuits; Random access memory; Read-write memory; Semiconductor device measurement; Timing;

English

ieee

Solid-State Circuits Conference, 1988. Digest of Technical Papers. ISSCC. 1988 IEEE International

San Francisco, CA, USA

conf

10.1109/ISSCC.1988.663688

663688