DocumentCode
1637742
Title
Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs
Author
Bandyopadhyay, Soumyadip ; Sarkar, Dipankar ; Mandal, Chittaranjan
Author_Institution
Indian Inst. of Technol., Kharagpur, Kharagpur, India
Volume
2
fYear
2015
Firstpage
827
Lastpage
828
Abstract
The initial behavioural specification of any software programs goes through significant optimizing and parallelizing transformations, automated and also human guided, before being mapped to an architecture. Establishing validity of these transformations is crucial to ensure that they preserve the original behaviour. PRES+ model (Petri net based Representation of Embedded Systems) encompassing data processing is used to model parallel behaviours. Being value based with inherent scope of capturing parallelism, PRES+ models depict such data dependencies more directly; accordingly, they are likely to be more convenient as the intermediate representations (IRs) of both the source and the transformed codes for translation validation than strictly sequential variable-based IRs like Finite State Machines with Data path (FSMDs) (which are essentially sequential control flow graphs (CFGs)). In this work, a path based equivalence checking method for PRES+ models is presented.
Keywords
Petri nets; embedded systems; formal specification; parallel programming; program interpreters; program verification; software architecture; source code (software); CFG; FSMD; PRES+ model; Petri net based models; Petri net based representation of embedded systems; architecture; behavioural specification; data dependencies; data processing; finite state machines with data path; intermediate representations; optimizing transformations; parallel behaviours; parallelism; parallelizing transformations; path based equivalence checking method; sequential control flow graphs; sequential variable-based IR; software programs; source codes; transformed codes; translation validation; Benchmark testing; Computational modeling; Data models; Embedded systems; Petri nets; Sparks; Equivalence checking; FSMD model; PRES+ model;
fLanguage
English
Publisher
ieee
Conference_Titel
Software Engineering (ICSE), 2015 IEEE/ACM 37th IEEE International Conference on
Conference_Location
Florence
Type
conf
DOI
10.1109/ICSE.2015.268
Filename
7203089
Link To Document