Title :
Cell-based test design method
Author :
Sakashita, Kazuhiro ; Hashizume, Takumi ; Ohya, Takashi ; Takimoto, I. ; Kato, Shuichi
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A cell-based test design method which is consistent with features of cell-based design is introduced. By improving shift register latches, a scan test for asynchronous circuits, as well as delay tests can be executed effectively. Also, by employing a test bus and a selector shift register configuration, a multiple scan-path test is realized attractively, which drastically reduces the execution time of the scan test. This results in the possibility of realizing a hierarchical test design in which the test vectors of module circuits are saved as library data and used in the preparation of the test vector of a newly developed chip and of the schematic and artwork data. It appears that the area overhead and the increase in test time are reasonable for future VLSI chips with the complexity of 1M transistors
Keywords :
VLSI; asynchronous sequential logic; automatic testing; cellular arrays; integrated circuit testing; logic CAD; logic testing; shift registers; ASIC; VLSI chips; area overhead; asynchronous circuits; cell-based test design; delay tests; execution time; hierarchical test design; library data; module circuits; multiple scan-path test; selector shift register; shift register latches; test bus; test time; test vectors; Circuit faults; Circuit testing; Delay; Design methodology; Laboratories; Large scale integration; Logic testing; Performance evaluation; Research and development; Shift registers;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82382
