A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

Author

Gruening, U. ; Radens, C.J. ; Mandelman, J.A. ; Michaelis, A. ; Seitz, M. ; Arnold, N. ; Lea, D. ; Casarotto, D. ; Knorr, A. ; Halle, S. ; Ivers, T.H. ; Economikos, L. ; Kudelka, S. ; Rahn, S. ; Tews, H. ; Lee, H. ; Divakaruni, R. ; Welser, J.J. ; Furukaw

Author_Institution

Infineon Technol. Corp., Hopewell Junction, NY, USA

fYear

1999

Firstpage

25

Lastpage

28

Abstract

Results are presented for a novel trench capacitor DRAM cell using a vertical access transistor along the storage trench sidewall which effectively decouples the gate length from the lithographic groundrule. A unique feature of this cell is the vertical access transistor in the array which is self-aligned to the buried strap connection of the storage trench (VERI BEST) and bounded by trench isolation oxide. The VERI BEST cell concept, process and electrical results obtained from 8F/sup 2/ test cell arrays at 0.175 /spl mu/m groundrules are described in this paper.

Keywords

DRAM chips; 0.175 micron; 16 Gbit; 4 Gbit; DRAM cell; VERI BEST; buried strap; self-aligned array; storage trench sidewall; trench capacitor; trench isolation oxide; vertical access transistor; Capacitors; Doping; Etching; MOSFET circuits; Microelectronics; Random access memory; Research and development; Testing; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.823838

Filename

823838