Title :
A novel cell-STP (storage node through plate node) cell-technology for multigigabit-scale DRAM and logic-embedded DRAM generations
Author :
Uh, H.S. ; Song, S.H. ; Park, B.J. ; Oh, J.H. ; Chun, Y.S. ; Kwak, D.H. ; Hwang, Y.S. ; Lee, K.H. ; Jeong, H.S. ; Chung, T.Y. ; Kinam Kim
Author_Institution :
Technol. Dev., Samsung Electron. Co. Ltd., Kyunggi, South Korea
Abstract :
A novel cell technology has been developed to overcome process issues related with successful downscaling of a DRAM memory cell and to produce a reliable and manufacturable cell. Storage node in the proposed cell is formed in a self-aligned manner through the plate node after the formation of plate node and capacitor dielectric. Considering the scalability of the novel cell and experimental results showing the charge storage capacitance of 25fF/cell, leakage current less than 1fA/cell, and excellent time-to-dielectric breakdown characteristics, it is expected that this novel cell technology can be a promising candidate for the 1Gb DRAM and beyond as well as logic-embedded DRAM.
Keywords :
DRAM chips; capacitance; cellular arrays; embedded systems; leakage currents; semiconductor device breakdown; 1 Gbit; capacitor dielectric; cell-STP; charge storage capacitance; leakage current; logic-embedded DRAM generations; multigigabit-scale DRAM; scalability; self-aligned manner; storage node through plate node cell-technology; time-to-dielectric breakdown characteristics; Capacitors; Dielectrics; Electrodes; Etching; Fabrication; Logic arrays; Logic devices; Random access memory; Research and development; Tin;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.823839
